1. Field of the Invention
The present invention relates to a squelch circuit, and in particular, to a squelch circuit that eliminates noise when there is no input to a receiver.
2. Background of the Related Art
As shown in FIG. 1, the related art squelch circuit 10 includes a programmable control network 20 and first and second N channel transistors 12,14 operated in accordance with differential input signals (V+,V-) that are connected in parallel with each other. First and second load resistances (R1,R2) are respectively connected to the sources of the first and second N channel transistors 12,14. A current source 16 is connected in parallel with the first and second N channel transistors 12,14.
The related art squelch circuit 10 further includes an N channel transistor 18 connected to the current source 16 and having a gate and a drain commonly connected, a first source resistance (R.sub.s3) connected between the source of the N channel transistor 18 and ground. A first comparator 30 has an inverting input terminal (-) connected to an input node of the second load resistance (R2) and a non-inverting input terminal (+) connected to an output node of the first load resistance (R1). A second comparator 32 has an inverting terminal (-) connected to the input node of the first load resistance (R1) and a non-inverting terminal (+) connected to the output node of the first load resistance (R2).
In the programmable control network 20, a first N channel source transistor 22 is connected in series with a second source resistance (R.sub.s1) between ground and an output node of the first load resistance (R1). A first N channel control transistor 24 is connected in series with a first variable resistance (R.sub.V1) between ground and the first load resistance (R1). A second N channel source transistor 26 is connected in series with a third source resistance (R.sub.S2) between ground and an output node of the second load resistance (R2). A second N channel control transistor 28 is connected in series with a second variable resistance (R.sub.V2) between ground and the second load resistance (R2).
The first through third source resistances (R.sub.S3,R.sub.S1,R.sub.S2) are matched and the first and second variable resistances (R.sub.V1,R.sub.V2) are controlled in accordance with an input control voltage signal (V.sub.CONTROL). Further, the gates of first and second N channel source transistors 22,26 and the first and second N channel control transistors 24,28 are commonly connected to the gate of the N channel transistor 18.
The operation of the related art receive squelch circuit will now be described. When differential input signals (V+,V-) employed in a twisted pair (TP) cable communication channel are inputted to respective gates of the N channel input transistors 12,14, the N channel input transistors 12,14 are operated. Accordingly, a current (I) starts to flow in the current source 16.
When the current (I) starts to flow in the current source 16, the N channel transistor 18 is turned on and maintained because the drain and gate of the N channel transistor 18 are commonly connected. Therefore, the current (I) flows through the N channel transistor 18. The gates of the matched N channel source transistors 22,26 and the N channel control transistors 24,28 are commonly connected to the gate of the N channel transistor 18 to form a current mirror. Since the first through the third source resistances (R.sub.S3,R.sub.S5,R.sub.S2) are matched, the current (I) flows only through the N channel transistor 18 and the N channel source transistors 22,26.
However, the currents (I) flowing through the N channel control transistors 24,28 are controlled in accordance with the values of the variable resistances (R.sub.V1,R.sub.V2). The variable resistances (R.sub.V1,R.sub.V2) are set in accordance with the input control voltage signal (V.sub.CONTROL). Accordingly, across the first and second load resistances (R1,R2) appears a voltage (V) dropped by as much as a threshold voltage (V.sub.TH) of the N channel input transistors 12,14. The voltage (V) can be expressed by the following equation. EQU V=(I+kI)R2(0&lt;k&lt;1) (1)
Thus, the threshold voltages are varied in accordance with the input control voltage signal (V.sub.CONTROL).
The first comparator 30 receives the voltage appearing at the input node of the second load resistance (R2) through its inverting input terminal (-) and the voltage appearing at the output node of the first load resistance (R1) through its non-inverting input terminal (+) and compares each voltage. Thereby, the first comparator 30 outputs a positive threshold voltage (V.sub.THP).
To obtain a high level output value from the first comparator 30, the voltage inputted through its inverting input terminal (-) must be higher than the voltage inputted through its non-inverting input terminal (+) by as much as the positive threshold voltage (V.sub.THP) outputted from the first comparator 30. To obtain a high level output value from the second comparator 32, the voltage inputted through its inverting input terminal (-) must be higher than the voltage inputted through its non-inverting input terminal (+) by as much as the negative threshold voltage (V.sub.THN).
As shown in FIG. 2, to set the values of the threshold voltages (V.sub.THN,V.sub.THP) in the squelch circuit 10, the programmable control network 20 of FIG. 1 can be replaced by a circuit having MOS transistors 52,54,56,58 connected in parallel with control transistors 52',54',56',58'. The control transistors 52', 54' 56' and 58' are turned on or off in accordance with gate driving signals (V.sub.CONTROL1 -V.sub.CONTROL4). The NOS transistors 52, 54, 56, 58 are connected in series to a current mirror transistor 50 and connected in parallel to a current mirror transistor 50'. That is, the control transistors 52',54',56',58' are turned on or off in accordance with the gate driving signals (V.sub.CONTROL1 -V.sub.CONTROL4), which are multi-bit digital inputs.
The operation of the control transistors 52', 54', 56', and 58' will now be described. For example, when the gate driving signals (V.sub.CONTROL1,V.sub.CONTROL3) are high and the gate driving signals (V.sub.CONTROL2,V.sub.CONTROL4) are low, the control transistors 52',56' are turned on and the control transistors 54',58' are turned off. The current mirror transistor 50 has its drain connected to its gate. Since the gate of the current mirror transistor 50 is connected to the gates of the control transistors 52,54,56,58, the control transistors 52,54,56,58 are kept turned on.
The threshold voltage (V.sub.TH) determined in accordance with the programmable control network 20 can be expressed by the following equation (2) in accordance with the current (I) determined by the current mirror transistor 50 and the current (4I) determined by the control transistors 52,52',56,56'. EQU V.sub.TH (I+4I)R1 (2)
When the control transistors of the programmable control network 20 determines the value of a current in accordance with a multibit digital input, the determined current value further determines the value of the threshold voltage of the squelch circuit 10 in accordance with the load resistances (R1,R2). Using the threshold voltage value, noise occurring in received data below the threshold voltage is eliminated. A related squelch circuit is disclosed in U.S. Pat. No. 5,408,694 issued on Apr. 18, 1995.
However, in the related art, the squelch circuit determining the threshold voltage only detects a level, but does not perform a timing check on an inputted signal. Input signal timing can cause an error in the inputted data detection. Accordingly, if a problem occurring in a transmission system causes a data delay, an obstacle or error is generated in the related art data transmission system.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.